Lorenzo De Carli

PLUG and other similar communication-exposed architectures allow the compiler significant freedom in mapping instructions to cores (and organizing the necessary communication). Compilers typically use heuristics to derive efficient mappings; however, such approach is complex, architecture-specific, and does not provide guarantees on the quality of the resulting mappings. Generalizing insights from the PLUG work, we designed a general framework that can produce schedules for any spatial architecture. In this approach, the architecture is described as a set of constraints on placement of computation on cores, and routing of on-chip data. Many constraints are common to most spatial spatial processors; support for a new processor can be implemented by adding a handful of constraints specific to its architecture. Our work on constraint-based scheduling was presented at PLDI 2013 and further detailed in our TOPLAS article.