Lorenzo De Carli

As part of my research I participated in the development of PLUG (Pipelined LookUp Grid) - a flexible network lookup module designed to be employed in network devices. The goal of our research is to create an “intelligent memory” that can perform network lookups (e.g. for IP forwarding) at hardware speed while being easily reconfigurable to support different data structures (hash tables, trees) and protocols. The core idea to achieve this goal is to express lookup algorithms as dataflow graphs incorporating both lookup data structures and computation. This algorithmic representation can then be compiled and mapped to an array of microcores (the PLUG hardware), which executes it efficiently in a pipelined fashion. The results of this work were the subject of our SIGCOMM 2009 paper. A detailed description of the PLUG hardware architecture was presented at PACT 2010, and PLUG-based solution for efficient packet classification was presented at ANCS 2011.

I then contributed to further research exploring alternative implementations of the PLUG dataflow concept. LEAP (ANCS 2012) replaces PLUG microcores with fixed-function units, diminishing latency and power consumption at the price of some flexibility. SWSL (ANCS 2013) is a compiler that can synthesize hardware lookup pipelines (expressed as PLUG-style dataflow graphs) from C++. In this case, the goal is to reduce hardware design/verification overhead while retaining high performance and low power consumption.